APPENDICES

Tools, setup, and the working vocabulary for this course.

Appendix A

The Mobile Architecture Workbench

Every tool this course needs, standing up in one sitting on any laptop — with a browser-only path for a locked-down machine and an optional route for students who own an Android device

Week 1 of an eight-week course cannot be spent installing things. A decision table keyed to what you actually have — administrator rights or none, Windows or macOS or Linux, an Android phone or no phone at all — routes you to one of three workbenches, and every one of them can complete every graded lab in this book. Covers the C++17 toolchain and why the measurement labs are compiled rather than interpreted, the Python analysis environment, the browser-only cloud path that needs no installation and no administrator rights, the timing and counter tools each platform offers, and the strictly optional Android path (developer options, the debug bridge, an on-device shell) for students who want to take a measurement on real mobile silicon. Closes with the verification pass that proves your workbench is measuring what you think it is — including the two calibration runs that catch a laptop whose power governor is quietly lying to you.

Appendix B

The SoC Reference Pack

How to read a system-on-chip block diagram and a specification table without being sold to — plus the captured datasets every lab in this book draws on

The reference you keep open all term. Part one teaches the skill the whole course rests on: reading a block diagram and a specification table the way an architect reads them, block by block, asking what each one is for, what it shares, what it contends for, and what the diagram is not telling you. It walks the anatomy common to every modern application processor — CPU clusters, GPU, neural and digital signal processors, image signal processor, display and video engines, memory controller, interconnect, secure subsystem, sensor hub, and modem — and gives the vendor-neutral vocabulary that lets you compare parts from different companies honestly. Part two documents every dataset shipped with the book: what each file contains, how it was produced, what it is safe to conclude from it, and what it is not. Every synthetic dataset is labeled as such on its first line, because a course about honest measurement cannot ship data that pretends to be something it is not.

Appendix C

The Measurement Kit

Benchmarking methodology, the statistics you actually need, the thermal soak protocol, and the report templates every lab in this course is graded against

Most bad architecture claims are not lies; they are honest measurements of the wrong thing. This appendix is the discipline that prevents that. Methodology first: what a microbenchmark can and cannot tell you, the difference between latency and throughput, warm-up and steady state, why the first run is always wrong, how to defeat a compiler that has optimized your benchmark away, and how to isolate a measurement from a laptop that is scaling its own clocks underneath you. Then the statistics — repetitions, medians against means, dispersion, and how to report a result with an uncertainty instead of a decimal point you cannot defend. Then the sustained-load protocol this book uses for every thermal claim, stated precisely enough that two students get comparable numbers. Closes with the templates: the measurement log, the comparison table, the architecture decision memo, and the capstone investigation report — each shown blank, then worked, then shown badly with the failure annotated.

Appendix D

The Grading Contract

How the grade is earned week by week, the rubric dimensions that recur on every lab, the three capstone-week rubrics in full, the pace table, the submission checklist, and the AI-use policy

No surprises in Week 8. The full contract: six weekly labs at forty-two percent, the Week 4 placement practical at eight, eight weekly quizzes at twelve, the Week 4 auto-graded checkpoint at ten, the capstone investigation at twenty, and the recorded technical briefing at eight. It explains the rubric dimensions that recur on every lab in this course — the measurement, the analysis, the citation-or-measurement line, the honest-uncertainty line, and the disclosure line — with the evidence that earns each one, and reproduces the three rubrics students most need before the week arrives: the Week 4 practical, the capstone investigation, and the technical briefing. Includes the week-by-week pace table stating what must be measured, written, and submitted by each Friday; the complete capstone submission checklist and repository structure; the artificial-intelligence use and disclosure policy with the required log format, written for a course where a model will happily invent a plausible cache-latency figure; the academic-integrity line; and a plain account of what fabricated or unrepeatable data costs on every rubric in this book, which is more than a wrong answer costs.

Appendix E

Glossary

The working vocabulary of mobile computer architecture, defined the way a practitioner uses it and cross-referenced to the week that teaches it

Every term this course uses as a term of art, defined precisely and pointed back at the week that earns it: system-on-chip, application processor, exception level, superscalar, out-of-order execution, branch prediction, single-instruction-multiple-data, vector length agnostic, big.LITTLE, DynamIQ, heterogeneous multiprocessing, thread migration, affinity, performance-per-watt, cache line, locality, replacement policy, coherence protocol, translation lookaside buffer, unified memory, bandwidth against latency, tile-based rendering, single-instruction-multiple-thread, shader core, neural processing unit, quantization, operator fallback, dynamic voltage and frequency scaling, clock and power gating, race-to-idle, thermal envelope, throttling, energy-aware scheduling, interconnect, direct memory access, sensor hub, hardware abstraction layer, root of trust, verified boot, trusted execution environment, secure element, memory tagging, side channel, instructions per cycle, sustained performance, and the emerging vocabulary of chiplets, advanced packaging, and edge inference.