Appendix E — Glossary

“Half of every architecture argument is two people using one word for two different things, and neither of them checking.” — an engineering adage

A vocabulary is compression, and here it is compression with money attached. When an architect says “that’s a peak number,” she has in three words named the measurement window, the thermal state, and which claim the figure can support. When an engineer says “the NPU and the display controller share a port,” he has predicted a class of bug before the code that produces it exists.

Where the industry uses a term loosely, this glossary gives you the sense this course grades. Where a real number exists and is stable, it is here; where it varies by vendor, generation or tier, you get the shape and a pointer to the datasheet — because refusing to state a figure you cannot source is the whole discipline of Chapter 8.

Read the three tables first. The confusion pairs, the units and the marketing vocabulary account for most of the wrong sentences in submitted work. The alphabet is a reference; the tables are the lesson.

How to read an entry. Bold term; an italic tag naming the week that earns it — the chapter that develops it, not one that mentions it; the practitioner’s definition; a bolded it is not clause where a term is commonly confused with another; a See also line where the neighbours matter. File names in code font are real — your six deliverable stems, or a shipped file in a chapter’s code/ directory.

The ten confusion pairs

Units, and the traps they set

A ratio without a baseline is not a measurement. “1.4× faster,” “30% more efficient,” “half the energy” — each has a hole in it until you name what it is a ratio of, under what conditions, on what hardware, over what window. A ratio inherits every confound of both numbers and hides them behind one tidy figure. Here it scores as an uncited figure, because that is what it is.

Marketing vocabulary, defined honestly

Two more. “Up to” on a clock, data rate or battery life is a best case measured under conditions nobody published — not false, not a measurement. And a single-number benchmark score is several workloads combined under a weighting somebody chose: an editorial judgment about what matters, presented as a measurement. Read the suite’s methodology page before citing its number.

A

AArch64 · Week 1 — The 64-bit execution state of the Arm architecture: 31 general-purpose registers X0–X30 (32-bit views W0–W30), with SP and PC handled separately and not among the 31; fixed 32-bit encoding; load/store architecture; four exception levels. A contract — everything below it is microarchitecture.

ACE / ACE-Lite · Week 2 — Arm’s coherent extensions to AXI: how caches on an Arm system actually agree, as against MESI/MOESI, which is the model you reason with. ACE-Lite-class interfaces let an I/O-coherent device participate without holding a cache. See also CHI.

Activity factor (α) · Week 5 — In P_dyn ≈ α · C · V² · f, the fraction of nodes switching per cycle, and the term software controls: fewer wasted operations, fewer discarded speculations, fewer bytes moved.

Affinity · Week 2 — A restriction on which CPUs a thread may run on (sched_setaffinity, taskset). Indispensable in measurement code and almost always a bug in shipping code, because a mask is a claim about a hardware topology that will outlive it. Apple platforms deliberately do not expose it. See also QoS class.

AI-usage note · Week 1; format in Appendix D — The honest disclosure ending every AI-assisted deliverable, submitted as ai-usage.txt: what you asked, what it produced, what you changed, how you verified. Not a confession and no penalty attaches; the penalty attaches to the unverified figure.

AMBA · Week 6 — Arm’s on-chip interface family: APB (simple, control registers), AHB (pipelined, modest peripherals), AXI (high-performance burst data path), ACE/CHI (coherent).

Amdahl’s law · Week 2 — speedup(p, n) = 1 / ((1 − p) + p/n). Its point is the ceiling the serial remainder imposes; its mobile correction is that n assumes n equal cores, which a heterogeneous CPU does not have. Convert to prime-equivalent cores first.

Application benchmark · Week 8 — A run of the real thing: an actual frame, an actual token, the actual camera pipeline. Representative and thoroughly confounded, it supports “under these conditions the user waits about X” and no sentence about why until counters are attached. It is not a microbenchmark, and a report that does not say which it ran has not reported a result.

Arbitration · Week 6 — How the interconnect decides who waits. Compare fixed priority (deadline-bearing clients first; a best-effort master can go to literal zero) against weighted fairness (proportional shares; every deadline-bearing client misses). Fairness is a defect when clients have unequal deadlines. See also Quality of service.

Arithmetic intensity · Week 4 — Operations per byte moved; the number that says whether a workload is compute- or memory-bound before you profile. Single-batch token generation sits at a famously low intensity, which is why widening a MAC array can buy almost nothing.

Armv9-A · Week 1 — The generation announced in 2021: SVE2 as a baseline, plus the Confidential Compute Architecture and its Realm world. Adoption is generational — direction of travel, not something present on a given part.

Array of structs / struct of arrays (AoS / SoA) · Week 3 — Two layouts for one dataset. A pass touching one field of every record wastes most of every line under AoS and uses all of it under SoA, at identical instruction count. Neither is universally right, which is why it is an architecture decision rather than a style rule.

Attestation — See Key attestation.

AXI · Week 6 — AMBA’s high-performance memory-mapped protocol and a mobile SoC’s main data path. Five independent channels — write address, write data, write response, read address, read data — so an initiator streams a burst behind an address; transactions carry IDs and those with different IDs may complete out of order, which is how a master keeps requests in flight. Also carries a per-transaction quality-of-service field.

B

Bandwidth · Week 3 — Bytes per second delivered in aggregate, exploitable only with many independent requests outstanding. Theoretical peak is arithmetic (bytes/s = MT/s × bus bytes) and a ceiling nobody reaches; achieved bandwidth depends on pattern, refresh, bank and row locality, requests in flight, and who else is on the bus. See also Latency, Little’s Law.

Bandwidth regulator · Week 6 — An interconnect mechanism metering a greedy master to a configured rate. Its companion is a latency target, raising a master’s effective priority as its deadline nears.

Batching · Week 6 — Coalescing small events so an expensive thing wakes once instead of many times: a sensor FIFO, one interrupt per DMA batch, network requests sent together. On a radio, batching beats compressing — the transfers are a rounding error next to the awake time. See also Tail, Wake-up.

Benchmark hygiene · Week 8; protocol in Appendix C — The six things a number must carry: a discarded warm-up, a stated steady state, repetitions reported as a median with dispersion, stated conditions, an optimizer barrier, like-for-like comparison. Skip one and you produce a specific, predictable lie.

big.LITTLE · Week 2 — Arm’s 2011 pairing of a performance and an efficiency cluster, through three successive models: cluster migration, the in-kernel switcher (core pairing, one virtual core per pair), and global task scheduling / HMP. HMP won completely; today the phrase almost always means HMP on an asymmetric CPU.

Binning · Week 4 — A tile-based GPU’s geometry pass: determine which tiles each primitive touches and write its transformed data into a per-tile bin (parameter) buffer in DRAM. It is the cost side of the tiling trade — per-triangle traffic bought in exchange for per-pixel traffic.

Biometric template · Week 7 — The stored representation of a fingerprint or face, whose architectural property is that it never leaves the secure subsystem: sensor path, matcher and store are all inside, and what crosses out is a yes/no plus a signed assertion.

Block diagram · Week 1; reading one is Appendix B — It looks like a parts list and is not. It is a map of who competes with whom for four shared resources: one memory system, one power delivery network and battery, one thermal budget, one interconnect.

Boot ROM · Week 7 — The immutable first boot stage, mask ROM fixed at fabrication with no update path, trusted for a physical rather than a cryptographic reason. Hence it is the smallest, most-reviewed code in the system, and why “unpatchable boot ROM bug” is a career-ending phrase.

Boot state · Week 7 — Android Verified Boot’s report — green, yellow, orange, red — of whether the chain verified against the device’s own keys, a user-installed key, or not at all. Note the gap: a chain rooted in a key an attacker provisioned still reports green.

Bottleneck · Week 1 — The shared resource under simultaneous demand that limits a workload. It is almost never inside a block. A bottleneck prediction — which resource, under which demand, and why — is the graded core of Lab 1 and of the capstone.

Branch prediction · Week 1 — Guessing a conditional’s direction so the front end can run ahead. On a phone it is also an energy story: work on the wrong path really executed — real transistors toggled — and was discarded.

Branch Target Identification (BTI) · Week 7 — Armv8.5-A: indirect branches may land only on instructions marked as legal landing pads. Like PAC and MTE, a class of mitigation rather than a patch.

Break-even residency · Week 5 — T = E_transition / ΔP: the minimum time in a low-power state for the saving to exceed the entry-and-exit cost. Sleep for less and you spent energy to save energy. It is why processors expose a ladder of idle states; Linux publishes each state’s exit latency and required residency under cpuidle.

Burst · Week 5 — The opening phase of a sustained load, dissipating far above sustained capability because thermal mass is absorbing the energy. It is a loan, and the loan comes due. A benchmark that finishes inside the burst has measured the chassis.

C

Cache · Week 3 — Fast, small, expensive storage. Memorize the shape — private and small at the top, shared and large at the bottom, a cliff before DRAM — and measure the sizes on the machine in front of you rather than reciting them.

Cache coherence · Week 2 — The guarantee that copies of a line in different private caches agree, which is what makes migration legal. Reason with MESI/MOESI; know the implementation is ACE/CHI plus a snoop filter — a directory at the coherency point tracking who might hold what, so requests need not broadcast. Its cost is bandwidth the GPU and NPU also want.

Cache line · Week 3 — What caches actually move: 64 bytes on essentially all Arm application processors and x86; some Apple designs use 128 (check sysctl hw.cachelinesize). It is why spatial locality is not optional and why coherence operates on lines rather than variables.

Cache maintenance · Week 6 — The explicit clean (before a device reads) and invalidate (after a device writes) required around a non-coherent device. Reverse the direction and you get intermittent corruption that survives every review, because the code looks symmetric — and it is why “zero-copy” is sometimes a clean-and-invalidate wearing a label.

Chain of trust · Week 7 — Boot ROM → bootloader stages → trusted OS and kernel → system image, each verifying the next. Its central property: trust is derived, never asserted. Immutability at the top is a fact about physics; below it, a fact about a check that ran milliseconds ago. Ask “derived from what?” until you reach a fuse or catch a loop.

Checkpoint (Week 4) · Chapter 4 — The auto-graded, cumulative knowledge check across Weeks 1–4, worth 10%. Not a Chapter 4 quiz; everything since Week 1 is in scope. The Week 4 practice quiz is ungraded.

CHI · Week 6 — Arm’s scalable coherent interconnect protocol, used where ACE does not scale.

Chiplet · Week 8 — One of several smaller dies replacing one large one: better yield, each die on its best-suited process, paid for in inter-die communication energy and packaging complexity. UCIe is the industry die-to-die standard effort. Further along in data-centre parts than in phone SoCs — be careful with adoption claims.

Clock gating · Week 5 — Stopping the clock to an idle block: α goes to zero and dynamic power collapses, but the block is still powered and still leaking. Entry and exit cost a cycle or two, so it happens constantly, in hardware, invisibly. It is not power gating.

Cold cache · Week 2 — What a migrated thread arrives to: empty private L1 and L2, untrained predictors and prefetchers. It is the floor under migration cost, measurable on one core by evicting between rounds — a control experiment needing no affinity.

Computational photography · Week 4 — Producing an image by computation over a burst rather than one exposure, on top of the ISP’s demosaicing, denoising, correction and tone mapping. It is why a phone camera outperforms its optics.

Confidential Compute Architecture (CCA) · Week 7 — The Armv9-A extension adding a Realm world. Its problem is TrustZone’s inverse: TrustZone protects the platform’s secrets from the rich OS; Realms protect a workload’s secrets from the platform.

Constant-time · Week 7 — Written so execution time and memory behaviour do not depend on secret data. Its cost is exact and permanent: you give up the best case forever so the worst case is never distinguishable from it. And its assumption is not absolute — a data memory-dependent prefetcher can reintroduce data-dependent traffic underneath perfectly constant-time source.

Contention · Week 1 — Simultaneous demand on a shared resource. Integration means sharing and sharing means contention; asking “what does this contend for” is the analysis, while “what is this for” is the parts list.

Cooldown · Week 8 — Idle time inserted between runs: a measurement choice, and the most powerful knob for making silicon look good. Five minutes between five-minute runs charts very differently from back-to-back runs, and both are honest as long as you say which.

Core ML · Week 4 — Apple’s on-device ML framework, which decides for itself among CPU, GPU and Neural Engine. Documentation at https://developer.apple.com/.

Counter multiplexing · Week 8 — What a PMU does when asked for more events than it has counters: time-slice them and scale the result up to an estimate. Two consequences everyone skips — a multiplexed count is an extrapolation whose error grows with variation, and two events on different slices were not observed simultaneously, so a ratio from them can be nonsense. Ask for a small event set that fits, then run again.

cpufreq / cpuidle · Week 5 — The Linux subsystems for frequency scaling and idle-state selection: the operating-point menu and governor, and the idle ladder with each state’s exit latency and required residency.

cpuset · Week 2 — A Linux partitioning of tasks into groups with restricted CPU sets; Android uses top-app, foreground and background to keep a sync out of the way of what the user is watching.

Crossover (interrupts vs polling) · Week 6 — The event rate above which polling costs less than interrupt servicing. A number, not a matter of taste — compute it from interrupt overhead, service time, wake energy and core power. It moves down when the handler gets fatter, so a sloppy driver drags a device into the polling regime early.

Crypto extension · Week 7 — Armv8 instructions (AES, SHA, PMULL) implementing expensive primitive rounds in hardware. Small feature, policy-sized consequence: when encryption is expensive it is optional and gets negotiated away; when nearly free, not doing it stops being defensible.

Cubic intuition · Week 5 — Because sustaining a higher f generally requires a higher V, and P ∝ V²f, power rises roughly as the cube of frequency over the range where voltage must track frequency. State it as an approximation and name the assumption: the last 20% of clock can cost far more than 20% of the power.

D

Dark silicon · Week 4 — Powered area idle for most workloads, which is what a fixed-function block is most of the time. It is the honest cost of specialization and the reason where the accelerator fleet stops is an open question.

Data memory-dependent prefetcher (DMP) · Week 7 — A prefetcher that inspects loaded values, notices pointer-shaped ones, and prefetches what they point to — and therefore a machine that dereferences data. Augury (2022) and GoFetch (2024), targeting Apple silicon’s DMP, showed this breaks a foundational assumption of constant-time cryptography.

Dataflow · Week 4 — In an NPU, which operand is held stationary in the MAC array — a weight, an output accumulator, an activation row — and therefore how many times each fetched value is reused. The defining design choice, because the win is moving each byte fewer times rather than owning more multipliers.

Deadline · Week 2 — The time by which work must finish. Here a deadline is a constraint, not a preference, which fixes the ordering: filter to the processors that meet it first, then minimize energy among the survivors. Reverse that and you get a result that is efficient and useless.

Decode · Week 1 — Turning instruction bytes into operations. Fixed-width encoding makes it cheap, and decode power is paid on every instruction, forever — the true and second-order half of the RISC argument.

Delegate · Week 4 — A framework component offloading part of a model graph to a backend: a GPU delegate, a vendor NPU delegate such as Qualcomm’s QNN or MediaTek’s NeuroPilot. As of 2026 delegation and vendor SDKs are the Android direction, NNAPI being deprecated; check https://developer.android.com/ rather than an old tutorial.

Deliverable stems · defined in Appendix D — The six file names this course submits and no others: report.docx, measurements.xlsx, soc-architecture-review.docx, placement-decision.docx, threat-model-report.docx, ai-usage.txt. A lab needing a second document gets a section of report.docx.

Dependency chain · Week 1 — A sequence in which each operation waits on the previous one’s result, so a wide superscalar core has issue slots it physically cannot use. Breaking one chain into several independent ones adds no transistor and no joule of hardware — the rare optimization with no cost.

Device memory · Week 6 — A memory type for peripheral register regions, restricting gathering, reordering and early write acknowledgement so a driver’s accesses arrive as written. One of three things between your code and a device, with volatile and barriers.

Dispersion · Week 8; required by Appendix C — The spread of repeated measurements, reported beside the median (the interquartile range is the usual choice). If the dispersion is comparable to the difference you are claiming, you have not measured the difference.

Display controller · Week 6 — Composes layers and drives the panel over MIPI DSI on a schedule the panel sets. The canonical hard real-time client of memory bandwidth — a late scanline is tearing or a dropped frame, with no retry — and the reason quality-of-service arbitration exists in mobile silicon at all.

Divergence · Week 4 — A branch splitting a lockstep group: the hardware runs one path with the other lanes masked, then the other. Cost is not max(a, b), it is a + b, for every lane — while a utilization dashboard reports the GPU busy throughout.

DMA · Week 6 — A device moving bulk data itself and interrupting once at the end, so the core sleeps through the transfer. Software builds descriptors in a ring; scatter-gather spans discontiguous pages. Two hazards: coherency (a non-coherent device needs cache maintenance) and containment (a raw physical address lets a device write anywhere — hence the SMMU).

DSP · Week 1 — A processor for streaming signal work on a continuous modest-rate input at very low power and duty cycle — audio, sensor streams, often the always-on listener. It contends for very little by design. Qualcomm’s Hexagon serves as both DSP and NPU.

DSU (DynamIQ Shared Unit) · Week 2 — Provides three things at once: the cluster’s shared L3, the coherency point where the snoop filter lives, and per-core power and frequency domains — the quiet revolution, since cores can now be gated individually. The shared L3 is why intra-cluster migration is much cheaper than crossing a cluster.

DVFS · Week 5 — Moving a core along a discrete menu of validated (frequency, voltage) operating points at run time. The scheduler’s other lever: placement says where, DVFS says how fast.

DynamIQ · Week 2 — Arm’s 2017 replacement for separate clusters: unlike core types in a single cluster behind a DSU, which is what makes fine-grained heterogeneous configurations practical.

E

Edge AI · Week 8 — Inference on the device. Drivers, durable: latency, privacy, offline operation, per-query cost. Limits, equally durable: memory footprint, sustained thermals, model quality at low precision — Weeks 3, 5 and 4 respectively. Everything else moves fast enough that you should trust your own measurement over any document, including this one.

Efficiency core · Week 2 — Built for the lowest joules per unit of work: narrower, shallower, smaller caches, lower top frequency, historically in-order or lightly out-of-order. It is not a small prime core — it holds a different office, and on peak single-thread throughput it will always look like a failure. A team that treats it as the lesser core schedules badly.

Efficiency knee · Week 5 — The operating point at which a fixed task costs the fewest joules. It exists because dynamic energy per task depends on voltage and not frequency (f cancels in E = P·t), while everything billed per second gets more expensive the longer you take. Their sum is a shallow U — and the knee moves: raise platform power and it climbs, because time got expensive.

eFuse / OTP · Week 7 — One-time-programmable fuses burned at manufacture, holding a root key or more commonly the hash of an authorized public key. Blown fuses do not un-blow and no mechanism to rewrite them exists.

eMMC — See UFS.

Energy · Week 5 — E = P × t, in joules, and the currency of this course, because a battery holds joules. Fixed task → joules per task; stream → performance-per-watt. Halving power while tripling run time is a 50% energy increase dressed as an efficiency win.

Energy-aware scheduling (EAS) · Week 2, closed in Week 5 — Linux placing a task using a per-platform energy model — the cores, their operating points, what each costs — so it costs the fewest joules for the performance required. Its existence proves placement, DVFS and thermals are one control problem, not three.

Exception level · Week 1 — EL0 applications, EL1 OS kernel, EL2 hypervisor, EL3 secure monitor and firmware; higher number, more privilege. Exception levels are orthogonal to TrustZone’s worlds — each world has its own EL0 and EL1 — and confusing the two axes is a common security-writing error.

F

False balance · Week 8 — A measurement that leads a reader to a conclusion the evidence does not support without any figure being false. The sharp form: a technically true number presented without its conditions is a false balance. Quote peak to a reader assuming sustained, or plugged-in to one assuming battery, and you fabricated nothing and misled anyway.

False sharing · Week 2 — Two threads on two cores writing two different variables that share a cache line, so the line ping-pongs at full coherence cost. Correctness-preserving, performance-destroying, invisible in the source, uncatchable by any test; padding fixes it entirely. Reason in lines, not variables.

Fault injection · Week 7 — Glitching supply voltage or clock at the right moment, or hitting the die with a laser, so an instruction fetches wrong or a comparison answers wrong. The classic target is the signature check: you need not forge a signature if you can make its branch go the other way.

FIPS 203 / 204 / 205 · Week 7 — The first NIST post-quantum standards, published August 2024: FIPS 203 (ML-KEM, from CRYSTALS-Kyber, key encapsulation), FIPS 204 (ML-DSA, from CRYSTALS-Dilithium, signatures), FIPS 205 (SLH-DSA, from SPHINCS+, hash-based signatures). This book gives you no sizes deliberately — read them at https://csrc.nist.gov/projects/post-quantum-cryptography and cite the document and table.

Fixed-function · Week 4 — Hardware implementing one pipeline with no programmability — an ISP, a video codec block, a display composition engine. It wins by not paying for generality; it loses the moment the standard changes.

Flash translation layer (FTL) · Week 3 — The logical-to-physical mapping inside a NAND device, necessary because flash is programmed in pages and erased in much larger blocks. Write amplification (a small logical write forcing a large physical one), wear levelling (spreading erases so no block dies first) and background garbage collection all follow — which is why flash latency has a long tail that averages hide.

Flush+Reload / Prime+Probe · Week 7 — The standard cache-timing techniques by which an attacker reads which lines a victim touched — the microarchitectural residue a speculative-execution attack leaves after architectural state has been correctly rolled back.

Form-factor divergence · Week 8 — One architectural vocabulary spanning wildly different budgets, where the budget determines the design: a wearable has a fraction of a watt and millimetres of thermal path, a phone sustains a few watts, a tablet’s extra area and mass raise the sustained point, an XR headset carries a hard low motion-to-photon budget on a human face. Place one workload on all four and the answer changes completely.

The Four Questions · Week 1, graded course-wide — Performance, energy, thermals, placement, asked in that order of every mechanism in this book. A student who can answer only the first has learned desktop architecture; the capstone grades holding all four at once over a block diagram you did not design.

FR1 / FR2 · Week 6 — 5G NR’s two frequency ranges: FR1 sub-6 GHz, FR2 millimetre wave. FR2 gives very wide channels over short range, penetrates obstacles poorly, and needs beamforming with dense antenna modules — costing power and volume, two things Week 1 said you do not have. Deployments are additionally non-standalone or standalone.

G

GIC · Week 6 — Arm’s Generic Interrupt Controller: prioritizes interrupts, decides which core receives each, handles masking and acknowledgement. It classifies by origin — software-generated, private per-core, shared peripheral — and recent versions add message-signalled interrupts so a system can carry more sources than there are wires.

GNSS · Week 6 — The correct general term for satellite positioning; GPS, Galileo, GLONASS and BeiDou are particular constellations, and a modern receiver uses several at once. Using “GPS” as the category name marks a writer who has not read a sensor datasheet.

Governor · Week 5 — The policy choosing a core’s operating point: performance, powersave, ondemand, conservative, userspace, and the modern schedutil.

GPU utilization · Week 8 — Typically the fraction of time the GPU had work queued. The same error as CPU utilization, only worse: it says nothing about whether shader cores were issuing or waiting on texture fetches, hides SIMT divergence entirely, and on a tile-based GPU the expensive thing — a read-back forcing tile memory to DRAM — appears as memory traffic, not busy time. The counter you want is bandwidth, not occupancy.

H

HAL · Week 6 — Android’s versioned contract between framework and vendor hardware code, defined in an interface description language (AIDL today, HIDL historically), with Project Treble having separated the two so they update on different schedules — see https://source.android.com/. Version skew across a HAL boundary is a recurring shape of integration failure.

Hard real-time · Week 6 — A deadline whose miss is a failure rather than a slowdown. On a phone the display controller and the camera receiver are the two, with no retry available — which is why they are guaranteed bandwidth first and everything else divides the remainder.

Harvest now, decrypt later · Week 7 — Why post-quantum migration is a present problem about a future capability: recorded traffic can be decrypted whenever the capability arrives, so any secret outliving that gap is already exposed. Note what nobody can honestly tell you — when.

Heterogeneous multiprocessing (HMP) · Week 2 — Every core of every class simultaneously visible to the scheduler, each thread placed individually. This is what distinguishes it from big.LITTLE’s earlier modes, under neither of which a big and a little core could be used at the same moment. HMP won because it is the only model that answers placement per thread.

Honesty line · Week 5 — The explicit comparison between what a short run would have reported and what a long run actually delivered, required in your Week 5 write-up: a ratio plus the conditions of both numbers.

Horowitz figures · Week 3 — From Mark Horowitz, “Computing’s Energy Problem (and what we can do about it),” ISSCC 2014 — the only quantitative literature citation licensed in this book. At 45 nm, as orders of magnitude: 32-bit integer add ≈ 0.1 pJ, 32-bit read from an 8 KB SRAM ≈ 5 pJ, 32-bit DRAM access ≈ 1300–2600 pJ. Absolute values move with node; the ratio — three to four orders of magnitude between moving a word and computing on it — has not been overturned, and the whole accelerator fleet follows from it. Always attribute it, always say “at 45 nm,” always say “order of magnitude.”

I

Immediate-mode rendering · Week 4 — The classic pipeline keeping colour and depth buffers in external memory, so traffic scales with overdraw. It is not simply “the old way” — Qualcomm’s Adreno can render directly or bin into tiles depending on the workload (FlexRender), making this a spectrum and sometimes a runtime decision.

Initiator / target · Week 6 — An initiator (or master) issues transactions — CPU cluster, GPU, NPU, display controller, camera receiver, modem DMA, storage. A target answers them — DRAM, the system-level cache, peripheral register blocks. Counting the initiators active during a use case is how you predict contention.

Instruction set architecture (ISA) · Week 1 — The contract: visible state, available operations, their meaning. Everything below it is microarchitecture — and two cores in one phone can be wildly different microarchitectures implementing the identical ISA, which is exactly what lets a thread migrate mid-execution.

Interconnect · Week 6 — The fabric routing, buffering, reordering and arbitrating transactions. It is the real system architecture: the fastest NPU on the die is slow if it cannot get weights. Reading a block diagram means tracing the lines and asking of each how wide, who else shares it, and what happens to me when they are busy.

Interface failure · Week 6 — A failure at the seam between two components that each passed their own tests. Most system failures are interface failures. The shapes: version skew; format, stride or colour-space mismatch; ordering and lifecycle bugs; deadline mismatch (one side assumes best-effort, the other has a deadline written down nowhere checkable); error semantics (A means “retry,” B treats every error as fatal).

Interrupt · Week 6 — A device signal diverting the CPU, routed on Arm by the GIC. The mobile default for one reason: sleeping is the whole point, and a polled core is an awake core. Not free — entry and exit overhead, a wake from a power-gated state, cache and pipeline damage, and the disturbance of deferring work from a short handler to a thread.

Interrupt livelock · Week 6 — Spending all your time taking interrupts and never running the code that drains the device: what happens above the crossover, and why Linux’s NAPI switches a driver to polling under load and back again.

IO-coherent · Week 6 — A device participating in coherence (on Arm, over an ACE-Lite-class interface) so the interconnect snoops CPU caches for it. A non-coherent device does not, and its driver must do cache maintenance by hand. Not every requester on a mobile SoC is fully coherent — which turns many “zero-copy” claims into questions.

IPC · Week 8 — Instructions retired ÷ cycles: the best first diagnostic, and uninterpretable in isolation. Read it relative to the core’s issue width — the same figure can be excellent on a narrow efficiency core and disappointing on a wide prime core running the same binary. Pair it with a miss rate before concluding.

IQR — See Dispersion.

ISP · Week 4 — The fixed-function pipeline between sensor and everything else: demosaicing, noise reduction, lens shading and distortion correction, tone mapping, multi-frame fusion. It does one pipeline enormously efficiently; that is the deal. Increasingly the ISP and NPU cooperate on one capture.

J

Joules per task · Week 5 — The correct efficiency metric for fixed work, as distinct from performance-per-watt for a continuous stream. Two views of one thing — but a claim about one is not a claim about the other.

K

Key attestation · Week 7 — A certificate chain rooted in a key provisioned at manufacture, asserting that a generated key lives in hardware, at what security level, under what policy — so a server learns something about silicon, not just about a protocol message. Its limit is every derived-trust mechanism’s limit: attestation rooted in a key an attacker provisioned convinces the server perfectly.

Keystore / StrongBox · Week 7 — Android’s hardware-backed key storage, StrongBox denoting dedicated secure hardware. The pattern to carry: the application never receives the key, it requests an operation. Compromise the app and you get the ability to ask, under the key’s policy — there is nothing to exfiltrate.

KV cache · Week 3 — A transformer’s per-layer key and value tensors for every token already generated: KV bytes = 2 × layers × sequence_length × kv_width × bytes_per_element, with kv_width = n_kv_heads × head_dim. It grows linearly with context length while the weights do not grow at all — negligible at short contexts, larger than the weights at long ones. Which is why “how big a model does this run?” is incomplete without “at what context length?”

L

L1 / L2 / L3 · Week 3 — Order-of-magnitude latencies to reason with, never to quote: L1 ≈ 3–5 cycles, L2 ≈ 10–20, L3 ≈ 30–60, DRAM ≈ 200–400+. Typical mobile sizes, as ranges because they genuinely vary: L1 instruction and data each 32–128 KB per core, L2 256 KB–4 MB per core or cluster, shared L3 behind the DSU 2–16 MB. A knee you found in your own data outranks any number either of us could recite.

Lab · the lab arc — The weekly graded build. Six at 7% each — Lab 1, Lab 2, Lab 3, Lab 5, Lab 6, Lab 7 — plus the capstone as Lab 8. There is no Lab 4: Week 4 carries the Placement Practical and the Checkpoint. Every lab is a measurement plus a judgment.

Latency · Week 3 — How long one dependent access takes, unhideable when the next address comes from the current load’s result. A pointer chase runs at latency; a sequential walk runs at bandwidth; same accesses, utterly different performance. “We have plenty of bandwidth headroom” is not an answer to a latency problem.

Leakage (static power) · Week 5 — Power dissipated simply by being powered on. It does not care whether you are doing anything — billed per second, not per operation — and it grows with temperature, a feedback loop thermal design must suppress. Leakage is why idle became a design problem.

Link register · Week 1 — X30, written by BL with the return address, which is why a non-leaf function must save it and a leaf need not — and why a return address spends time on the stack, the exposure Pointer Authentication closes.

Little’s Law · Week 3 — bytes in flight = bandwidth × latency, the best back-of-envelope tool in the memory chapter. Divide by the line size and you learn how many outstanding line requests a peak bandwidth figure actually demands. A dependent chase gives you one, which is why a program can idle a fast memory system while using well under a percent of it.

Load/store architecture · Week 1 — Arithmetic operates only on registers; memory is touched only by explicit loads and stores.

Locality · Week 3 — Temporal: you will touch this datum again soon. Spatial: you will touch its neighbours soon, so the rest of the fetched line is not wasted. Temporal locality is a nice-to-have; spatial locality is the tax structure of the machine, because the line is 64 bytes whether you use 4 of them or 64.

Lockstep group · Week 4 — The GPU threads executed together off one instruction stream: Nvidia “warp,” AMD “wavefront,” Arm Mali “warp,” Qualcomm Adreno “wave.” Width varies by vendor and generation, commonly somewhere in the eight-to-128 range; never state a specific mobile width without a datasheet.

Low-memory kill · Week 3 — A phone’s answer to sustained memory pressure: it terminates background processes rather than paging to storage, because NAND has finite endurance, flash writes are slow and variable, and a page-in is microseconds-to-milliseconds against tens of nanoseconds for DRAM. Android has additionally used compressed in-memory swap; names and policies differ by platform and generation. The consequence: your process’s continued existence is a resource the system may reclaim.

LPDDR · Week 3 — The low-power DRAM family. “LP” buys lower supply and I/O voltages (a direct V² win), aggressive low-power states, wider internal prefetch, and packaging — often package-on-package, sharing the SoC’s thermals. LPDDR5X is the 2024–2025 mainstream with data rates commonly quoted around 8533 MT/s and higher bins above; treat the number as hedged.

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MAC array · Week 4 — The grid of multiply-accumulate units at an NPU’s centre, arranged so a value loaded once is consumed by many units. It is not why an NPU wins — CPUs and GPUs have multipliers too. The dataflow around it is.

mAh · Week 5 — Milliamp-hours: a charge, not an energy, becoming energy only when multiplied by a voltage — Wh = mAh × nominal volts / 1000. Is 5000 mAh bigger than 4500? Only at the same nominal voltage. Single-cell lithium-ion nominal voltages are commonly quoted somewhere in the 3.7–3.9 V range; the real figure is on the cell’s datasheet.

Measurement log · defined in Appendix C, required by every lab — The per-lab record submitted as measurements.xlsx: what you ran, on what, how many repetitions, the median, the dispersion, the conditions. It is the difference between a result and a rumour.

Median · Week 8 — The reported centre of an odd number of repetitions (31 is a good default for a fast kernel), required because it resists the one run where a background process woke up. Report the median, not the minimum: on a thermally limited device the fastest run is the coldest run, and coldness is a property of the last four minutes rather than of the silicon.

Memory barrier · Week 6 — On AArch64: DMB orders accesses around it, DSB additionally waits for completion, ISB flushes the pipeline so later instructions see new system state. Barriers exist because writing a descriptor and then a device’s “go” bit is only correct if those stores reach the bus in that order. volatile is not a barrier.

Memory-bound · Week 3 — Limited by delivery rather than arithmetic. The canonical case: generating a token requires reading essentially all weights once, so tokens/s ≤ bandwidth ÷ weight bytes is a ceiling that does not move when you add multipliers. Establish whether you are memory-bound before optimizing arithmetic.

Memory hierarchy · Week 3 — Registers → L1 → L2 → L3 → system-level cache → DRAM → flash, each step a multiple rather than a margin, with a cliff before DRAM and a change of regime entirely at flash. Two mobile-specific facts a desktop course omits: the DRAM is often packaged on the SoC and shares its thermal environment, and there is no swap-to-disk safety net.

Memory-level parallelism (MLP) · Week 3 — How many misses a core can have in flight. With the prefetchers it is the bridge converting bandwidth into apparent latency reduction. A sequential walk has enormous MLP; a pointer chase has exactly one.

Memory-mapped I/O · Week 6 — Device registers occupying physical address space, so a load or store is a bus transaction that makes a device do something: reading a status register can clear it, writing a command register can start a DMA. It breaks the compiler’s and the core’s ordinary assumptions, hence volatile, barriers and a Device memory type.

Memory Tagging Extension (MTE) · Week 7 — Armv8.5-A: a 4-bit tag per 16-byte granule of memory with a matching tag in the pointer’s top byte (relying on top-byte-ignore); a mismatch faults. It catches use-after-free and buffer overflow in hardware, at the bad access rather than by luck at a later crash. A class of mitigation, and its cost — tag storage and check cycles — depends on implementation and mode, making it exactly the figure you measure rather than quote.

Memory wall · Week 3 — The growing processor-memory speed gap, named in Wm. A. Wulf and Sally A. McKee, “Hitting the Memory Wall: Implications of the Obvious,” ACM SIGARCH Computer Architecture News, 1995. Thirty years on the implications remain obvious and remain the most consistently ignored thing in a graduate performance analysis.

MESI / MOESI · Week 2 — The teaching model: each line is Modified, Exclusive, Shared or Invalid, with MOESI adding Owned so a dirty line can be shared without a write-back. Carry two layers — MESI/MOESI is what you reason with, ACE/CHI with a snoop filter is what is on the die.

Microarchitecture · Week 1 — Everything below the ISA contract: pipeline depth, issue width, reorder capacity, cache sizes, predictor structures. Invisible to the contract, and where vendors differentiate.

Microbenchmark · Week 8 — A run isolating one mechanism: unconfounded, and trivially easy to make precisely wrong — a working set that accidentally fits in L2, a stride aligned with associativity, a compiler that vectorized the loop you thought was scalar. It supports “this mechanism, in isolation, costs about X” and no sentence about application time. The professional shape is application → counters → microbenchmark → application again.

Migration · Week 2 — Moving a running thread to another core: legal because coherence guarantees it, and it costs because the destination’s private caches are cold, its predictors untrained, the scheduler pays run-queue work and an inter-processor interrupt, and the destination may need to ramp frequency. The shared L3 survives within a DSU. Do not report thread-creation overhead as migration cost — they arrive mixed and must be separated.

MIPI CSI-2 / MIPI DSI · Week 6 — Camera-to-SoC and SoC-to-panel interfaces: same physical family, opposite directions. CSI-2 is sensor-paced with no back-pressure, which is what makes the camera a hard-real-time consumer of bandwidth.

Misprediction penalty · Week 1 — Typically on the order of ten to twenty cycles on a deep out-of-order core, though entirely microarchitecture-dependent. The mobile reframing: those instructions ran and the result was discarded, so a misprediction is not merely a latency event, it is a pure energy loss.

Modem (cellular) · Week 6, security in Week 7 — Not a peripheral: a large subsystem with its own DSPs, control processors and real-time software stack. It is a computer running its own operating system next to yours. Three consequences: a bus master with real-time needs; frequently the largest single power draw during sustained transfer, heating the chassis near the antennas; and an attack surface with memory access, whose containment is a property of the fabric and the SMMU rather than of the modem.

Motion-to-photon · Week 8 — Latency from head movement to the corresponding photons, and the hard constraint shaping XR silicon. Budgets in the low tens of milliseconds are widely stated as a design target — a target, not a specification.

MPKI · Week 8 — misses ÷ (instructions ÷ 1000). Prefer it to a miss rate when comparing two versions of one program, because a rate over accesses can improve while absolute stall time gets worse.

MT/s · Week 3 — Megatransfers per second, the number the LPDDR spec quotes. It is not MHz, and it is not bandwidth until multiplied by the bus width in bytes. Going from a 64-bit to a 256-bit interface at the same data rate quadruples bandwidth without changing DRAM generation — width, not generation, usually bought the bandwidth, and width costs pins, board area, controller area and power, which is exactly why a phone lacks it and a laptop has it.

Multi-frame fusion · Week 4 — Combining a burst of exposures into one image with better dynamic range and less noise than any single frame; a substantial, bursty consumer of bandwidth and ISP throughput.

N

NAND flash · Week 3 — Programmed in pages, erased in much larger blocks, so a page cannot be overwritten in place — whence the flash translation layer. Two consequences a desktop architect forgets: storage is a thermal and power actor (a sustained write heats up and can throttle), and it sets your cold-start time — loading a multi-gigabyte model file is seconds, not milliseconds, and no NPU fixes that.

NEON (Advanced SIMD) · Week 1 — The baseline SIMD on essentially all 64-bit Arm application processors: registers V0–V31, each fixed at 128 bits. Because the width is architectural it enters your source code — main loop, scalar tail, horizontal reduction, and a rewrite for a wider machine. Give a NEON binary a wider machine and it runs correctly at the old width until somebody recompiles.

Network-on-chip · Week 6 — Routers, links and packets replacing a crossbar once its area and wire length become intolerable. Topology is not abstract: a wire crossing the die costs area, energy per bit and latency, so where a block sits is part of its performance specification.

NNAPI · Week 4 — Android’s former neural-network acceleration API, deprecated in Android 15 (API level 35). For a decade it was the answer to “how does an app reach the NPU,” and it is no longer that answer — which makes it the fastest way to spot an obsolete tutorial, or a model whose training data froze mid-transition.

NPU · Week 4 — A matrix engine for low-precision multiply-accumulate wrapped in a dataflow that maximizes on-chip reuse. Say the defining sentence until it is instinct: an NPU is a machine for not moving data. Names to use correctly as of 2026: Apple Neural Engine, Qualcomm Hexagon, MediaTek APU, the TPU-derived block in Google Tensor SoCs, Samsung Exynos NPU, Arm Ethos NPU IP. Learn the names; do not learn the marketing numbers attached.

NS bit · Week 7 — The non-secure bit propagating with transactions out of the core and across the interconnect, so memory, peripherals and DMA masters can each be marked secure or not. It is why TrustZone is a system partition: a Normal-world read of secure memory is refused by the fabric, not by a software check.

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Operating point (OPP) · Week 5 — A validated (frequency, voltage) pair. The hardware exposes a discrete menu characterized in silicon, not a continuum; DVFS walks a core up and down it and the governor chooses.

Operator fallback · Week 4 — The classic accelerator disappointment. A runtime finds one operator it cannot implement and does not fail — it partitions, running the rest on the CPU, so tensors round-trip repeatedly per inference. The result is an “accelerated” path slower and hungrier than pure CPU while every dashboard reports the accelerator engaged. Response: profile the partition, ask which operators were actually placed, and always keep a plain CPU baseline as a control.

Optimizer barrier · Week 3, enforced in Week 8 — The construct stopping a compiler from deleting a benchmark whose result nobody uses: an empty asm volatile with a register constraint and a "memory" clobber, or a write to a volatile sink. If a result looks impossibly good, suspect the optimizer before you believe the machine, and sanity-check by doubling the input size.

Out-of-order execution · Week 1 — Executing as operands become ready, retiring in program order. Much better on memory-stalled code, worse per instruction in energy, often better per task, and expensive in area and leakage — which is why efficiency cores carry less of it.

Overdraw · Week 4 — Fragments shaded per final pixel. Immediate-mode traffic scales with it; tile-based traffic does not, because repeated shading costs tile-memory bandwidth rather than DRAM bandwidth. Sweeping overdraw is how you find where binning stops paying.

Overlay plane · Week 6 — A fixed-function display-controller path reading layers directly during scanout, so no intermediate buffer is written. When overlays work the GPU stays asleep and a whole DRAM round trip never happens; when they do not, the GPU wakes and the frame costs several times more energy for a pixel-identical result.

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Package-on-package · Week 3 — DRAM packaged directly atop the SoC: short traces, good signal integrity, low z-height — and DRAM that shares the SoC’s thermal environment. Long standard in phones.

Peak · Week 5 — What a device delivers before the thermal transient ends, while the chassis is still absorbing heat. A true number about a cold device, and the right claim for genuinely bursty work — unlocking, launching an app, one turn of a conversation. The wrong claim for a game, an export, a navigation session, a long generation. Quote both or quote neither, and state the conditions.

PELT · Week 2 — Per-entity load tracking: the Linux estimate of a task’s utilization over time, and the signal both schedutil and EAS consume. Some vendor kernels historically used WALT with different responsiveness.

Performance Monitor Unit (PMU) · Week 8 — Arm’s hardware counters: cycles, instructions retired, cache references and misses per level, TLB misses, branches and branch misses, stalled cycles. Counts of things that physically happened — until you ask for more events than there are counters, at which point they become extrapolations.

Performance-per-watt · Week 2 — The efficiency metric for a continuous stream, and the metric that decides a mobile CPU design review. Its trap: maximizing it and meeting a deadline are different objectives, so frame work on the most efficient core is efficient and useless if the frame misses. Deadline first as a constraint, energy second as the objective — never the reverse.

Physical possession · Week 7 — The adversary capability distinguishing mobile from server threat modelling. A seized server is generally considered lost; a phone is expected to be seized and is nevertheless expected to keep its secrets. Note also that the software attacker and the physical attacker gain different things from the same broken link — a mutable boot ROM is unreachable by software and total on a bench.

Pipelining · Week 1 — Overlapping fetch, decode, execute, memory and write-back so throughput approaches one instruction per cycle. Depth buys frequency and costs a larger mispredict penalty and a higher voltage to sustain the clock.

Placement · Week 4 — The fourth of The Four Questions: which processor should do this work at all? It widens through the course — among CPU core classes in Week 2, among processors in Week 4, among power domains in Week 6 (the sensor hub’s whole point), and among security domains in Week 7, where the fast answer and the trustworthy answer are frequently not the same processor.

Placement Practical · Chapter 4 — Week 4’s take-home, worth 8%, standing in place of a weekly lab. It produces placement-decision.docx and report.docx defending an assignment of six workloads with the energy arithmetic, an account of what operator fallback does to a naive assignment, the workload whose right answer is a block not in the dataset, and an explicit statement of what you would need to measure on real hardware to confirm any of it.

Placement table · Week 4, required in the capstone — Four columns — workload → chosen processor → why → what it costs — submitted as placement-decision.docx. Not a spreadsheet of scores: every row is an argument, and a row without a defensible “why” and an honest cost is a preference. A placement table without its stated latency budget is meaningless, because tightening the budget moves the correct answers with no hardware changing.

Platform power · Week 5 — Everything drawing current while your task runs that is not your task: display, radios, memory controller, always-on rails. Billed per second, so it makes time expensive — which is why the efficiency knee climbs when the screen is on, and why the efficiency ordering of core classes is not absolute; it depends on what else is awake.

Pointer Authentication (PAC) · Week 7 — Armv8.3-A: a pointer is signed with a keyed MAC in its unused upper bits and authenticated before use, defending return addresses and function pointers. It attacks the reuse half of memory-corruption exploitation — you can still corrupt a pointer, you just cannot forge a valid one.

Polling · Week 6 — Asking a device repeatedly rather than waiting for an interrupt: deterministic, very low latency, and an energy catastrophe at low event rates because a polled core is an awake core. It is not automatically wasteful — above the crossover it uses less energy and has lower latency.

Post-quantum cryptography (PQC) · Week 7 — Cryptography resistant to a large quantum computer. Mobile consequences land on all four questions: sizes (keys, ciphertexts and signatures substantially larger than elliptic-curve ones, pressuring a small, expensive secure element), wire bytes (more per handshake, and radio energy is dominated by awake time, so extra bytes cost twice), and compute and placement (more expensive operations pushing toward acceleration nobody budgeted area for).

Power · Week 5 — Energy per unit time, in watts. Dynamic power P_dyn ≈ α · C · V² · f — note the square on voltage, the most important exponent in mobile computing. Static power is leakage. Power is not the currency; energy is.

Power gating · Week 5 — Cutting a block’s supply so leakage goes away too — but an unpowered block forgets everything, so entering costs saving state and leaving costs restoring it, refilling caches and relocking PLLs. Expensive on both ends, which is exactly why break-even residency exists. It is not clock gating, which is cheap, constant, invisible to software, and leaves leakage untouched.

Precision · Week 4 — The numeric format of weights and activations: FP32 (4 bytes), FP16/BF16 (2), INT8 (1), INT4 (0.5). The memory consequence is exact arithmetic: INT8 is precisely 4× smaller than FP32, INT4 precisely 8×. The accuracy consequence is irreducibly empirical and must be measured on your model, your task, your evaluation set. Keeping the two halves separate is most of the skill.

Prefetcher · Week 3 — Hardware detecting a pattern and issuing loads before you ask. It converts bandwidth into apparent latency reduction on predictable patterns and does nothing for a randomized chase; the gap between your two curves is your prefetcher and MLP, quantified.

Primary source · course-wide; policy in Appendix D — A vendor specification page, an architecture reference manual, a standards document, or your own measurement with the method recorded. Every figure in every submitted document carries one, with a retrieval date. An uncited figure scores zero on its line; a fabricated one fails the integrity line outright. This is the operational half of use it to explain, never to source.

Prime core · Week 2 — The largest, widest, deepest, highest-clocking core in a cluster. You buy it to satisfy a latency deadline no amount of parallelism can satisfy, you pay in area, power and leakage, and you keep it asleep as much as you can. A typical 2024–2025-generation Arm flagship phone CPU is commonly one prime, three to five performance and two to four efficiency cores, often totalling eight — the common shape, not a rule, since some 2024-generation flagships shipped all-large configurations with no small cores.

Prime-equivalent core · Week 2 — Each core class weighted by relative throughput and summed; the unit you must convert to before Amdahl arithmetic on a heterogeneous CPU. The gap between the physical count and the equivalent count is the gap between the number on the box and the machine you have.

PTQ (post-training quantization) · Week 4 — Quantizing a trained model afterwards, usually with a small calibration set to choose scales: fast, no training pipeline, where you start. It is not QAT. The choice is empirical — try PTQ, measure, escalate only if the measurement says you must.

Q

QoS class (Apple platforms) · Week 2 — The intent-based alternative to affinity: QOS_CLASS_USER_INTERACTIVE, …_USER_INITIATED, …_UTILITY, …_BACKGROUND. You declare intent; the system decides placement. An affinity mask is precise and will outlive the topology it describes; a QoS class survives the hardware because it describes the workload. Express intent in shipping code; take control only in measurement code.

Quality of service (QoS) · Week 6 — Interconnect mechanisms letting the fabric distinguish clients with deadlines: a per-transaction QoS field on AXI, bandwidth regulators, latency targets, sometimes a private port or reserved cache allocation for the display controller. One idea in different clothes: the fabric must know which client has a deadline, because the clients cannot tell each other.

Quantization · Week 4 — Storing and computing in fewer bits. Symmetric integer quantization is three operations: pick a scale (scale = max(|w|) / 127), quantize (q = clamp(round(w / scale), −127, 127)), dequantize (w' ≈ q × scale). The choice that matters more than it looks is per-tensor versus per-channel scales: one loud channel poisons every quiet channel sharing its scale, and per-channel scales are the entire fix. Because inference is usually memory-bound, quantization is a bandwidth technique before a capacity one.

Quantization-aware training (QAT) · Week 4 — Simulating quantization during training so the network learns weights that survive it, recovering accuracy PTQ loses at the cost of a training run. It is not “better quantization” — the same target format by a more expensive route, and whether you need it is a measurement about your model and your task.

Quiz · weekly; contract in Appendix D — Two different items, and confusing them is expensive. The short “Check Your Reps” check on each chapter page is an ungraded self-check; take it before you move on. The graded item is a separate randomized quiz in Canvas — eight of them, 1.5% each, 12% of the grade, same material from a larger pool, so a retake is real practice rather than memorization. Week 4 is the shape people miss: its graded knowledge check is the cumulative Checkpoint, which stands in place of that week’s ordinary quiz, and the Week 4 practice quiz is ungraded.

R

Race-to-idle · Week 5 — Finishing fixed work fast at a high operating point and then dropping into deep sleep. It is not a law. It wins when the work is fixed and finite, a genuinely deep idle state exists, being awake is expensive relative to the core, and the target point is at or below the efficiency knee. It loses past the knee, on a continuous stream with no idle to race to, when something else keeps the platform awake, or when going fast heats the device into throttling and you end up slower and poorer.

Realm world · Week 7 — The third world added by Armv9-A’s CCA, alongside Secure and Non-secure, protecting a workload’s secrets from the platform. Adoption is generational.

Render target read-back · Week 4 — Sampling or reading the framebuffer you are drawing into on a tile-based GPU: one line of application code, and a bandwidth and energy catastrophe, because it forces the finished tile out to DRAM and often pulls the target back in. Do not read back a render target, and do not clear or load one you did not need.

Replacement policy · Week 3 — Which way in a set gets evicted. Use LRU as your model; real caches use cheaper approximations, pseudo-LRU and re-reference interval prediction being the usual families. Reason statistically: you cannot promise the hardware keeps a line, only make it likely.

Residual risk · Week 7 — What a mechanism does not cover, stated per asset. It is where the grade lives in threat-model-report.docx, because anyone can list mechanisms — the list is on every vendor’s marketing page. A threat model that claims to stop everyone is a threat model nobody reviewed.

RISC vs CISC · Week 1 — What is true: load/store, fixed-width encodings and large regular register files simplify decode, and decode power is paid on every instruction, which mattered enormously at a one-watt budget. What is no longer true: modern high-performance x86 decodes into micro-operations executed out of order, so the back ends look far more alike than the slogan suggests; x86 ships in fanless laptops and Arm in servers, so the ISA is not destiny; and AArch64 has scaled-index addressing, pair load/store and an instruction that performs an AES round, none of it “reduced” in the 1980s sense. The honest summary: the instruction set is a real but second-order effect; the first-order effects are the memory hierarchy, the accelerator fleet, and the power and thermal budget.

RISC-V · Week 1, revisited Week 8 — An open, royalty-free ISA. Base RV32I/RV64I; the common application-class bundle is RV64GC. Privilege modes M (machine), S (supervisor), U (user) with an optional hypervisor extension — compare with Arm’s EL3/EL1/EL0, do not equate. As of 2026 it ships in volume in embedded and accelerator roles, including as control cores inside SoCs that are otherwise Arm; it is not the application-processor ISA of mainstream phones, and this book will not predict whether that changes. Profiles at https://riscv.org/.

Rollback protection · Week 7 — Recording a minimum acceptable version and refusing older images even correctly signed ones. Signature verification answers “did the vendor produce this?” and says nothing about “is it still safe?” Without it an attacker installs last year’s genuine, signed, known-vulnerable firmware; every check passes and the boot state is green. It is the difference between authenticating the author and authenticating the version.

Root of trust · Week 7 — The immutable first stage plus fused keys, trusted for a physical rather than a cryptographic reason, from which everything else is derived. Ask “derived from what?” until you reach a fuse or catch a loop; circular trust is astonishingly common and always sounds fine on the first pass.

RVA23 · Week 1 — The RISC-V application-processor profile ratified in 2024, making the vector extension mandatory for compliant application processors. That matters more than any instruction: a feature only some implementations have cannot be used by a shipped binary without runtime dispatch, meaning writing and testing the code twice. A profile converts “you might have vectors” into “you have vectors.”

RVV · Week 1 — The RISC-V “V” vector extension, version 1.0 ratified November 2021. Vector-length agnostic by a different route than SVE: vsetvli requests an element count and the hardware returns how many it will do this pass. VLEN is implementation-defined.

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schedutil · Week 5 — The modern Linux cpufreq governor, driven by the scheduler’s own utilization signal rather than a separate sampling loop. That input is the architectural point: with schedutil, placement and frequency became one control problem.

Secure boot · Week 7 — Each stage cryptographically verifying the next before transferring control. Note precisely what it does not do: nothing about a device that boots perfectly and is exploited at runtime through the browser. It defends against persistence, not against compromise — its promise is that however badly today went, a reboot returns you to code the vendor signed. Say the narrow thing in your report.

Secure element (SE) · Week 7 — A separate tamper-resistant chip descended from the smart card, used for payment credentials and similar. It is not a TEE. A TEE is isolation by mode on the application cores, reaching system-wide through the NS bit and sharing microarchitecture with the attacker; an SE is isolation by silicon, sharing almost nothing, reaching only what it holds, deliberately modest in performance, paid for in area and standby power. Different questions: a TEE enforces a system-wide policy, an SE holds a small secret against a determined adversary with the board on a bench. Most devices use both, and the engineering is deciding which asset goes where.

Secure Enclave · Week 7 — Apple’s separate security coprocessor with its own boot ROM and memory: the widely cited example of isolation by silicon and the clearest contrast with TrustZone’s isolation by mode. Google’s Titan M-class chip is another commonly cited security processor.

Secure world / Normal world · Week 7 — TrustZone’s two partitions, each with its own EL0 and EL1, with EL3 firmware mediating the crossing. That crossing is not a function call but a controlled, narrow, expensive transition, and its narrowness is the point: the attack surface of a TEE is exactly the size of its interface.

Sensor fusion · Week 6 — Combining accelerometer, gyroscope, magnetometer and other MEMS sensors into an orientation estimate, because each alone is useless: an accelerometer cannot tell gravity from acceleration, a magnetometer is confused by the device’s own metal, a gyroscope drifts. Continuous low-rate work that must never stop — hence the sensor hub.

Sensor hub / always-on processor · Week 6 — A small, very-low-power core (often a DSP, sometimes Cortex-M-class) with its own memory and firmware, keeping sensors, gestures and wake-word detection alive while the application processors sleep. The architectural answer to always-on without always-awake, and a different kind of placement answer: not a cheaper core but the one island allowed to stay powered. The cheapest work is work that does not require the expensive thing to be awake at all.

Set-associative · Week 3 — An address selects a set, and the set holds a fixed number of ways. The mechanism behind conflict misses: with S sets and 64-byte lines, addresses differing by a multiple of S × 64 collide, so a power-of-two-strided walk thrashes a few kilobytes of distinct lines — and padding an array to make it bigger can make the loop dramatically faster. The machine is not haunted; it is indexed.

Shader core · Week 4 — The programmable GPU engine running vertex, fragment and compute stages. Mobile compute paths: Vulkan compute (broadly available on Android), OpenCL (vendor-dependent availability — check, do not assume), Metal on Apple platforms, WebGPU in the browser, which is the path that works on Workbench B with nothing installed.

Side channel · Week 7 — Anything a system does differently depending on a secret: time, cache state, power draw. The law of the chapter, worth memorizing verbatim: any optimization that makes behaviour depend on data is a potential side channel, and mitigating it costs performance. That tradeoff cannot be engineered away, only decided — by a person, for a product, against a named adversary. Branch prediction was just a performance optimization. So was caching.

SIMD · Week 1 — One instruction, one decode, one issue slot, N results in one thread on one core; decode and issue energy amortizes across the lanes, making it one of the few mechanisms that improves performance and energy per unit of work at once. It is not SIMT — no threads, no divergence, bounded by register width and core count.

SIMT · Week 4 — Many independent threads executed in lockstep groups off one instruction stream: you write the code for one element and the hardware runs it for thousands. It is not SIMD, and the difference that bites is divergence.

Skin-temperature limit · Week 5 — The ceiling on sustained dissipation, set by what a human hand can comfortably hold, not by what the silicon survives. Junction temperatures a die tolerates would burn a hand, so the silicon is nowhere near its limit when a phone throttles — the user is. Sustained dissipation for a phone-sized device lands on the order of a few watts against tens to hundreds for a plugged-in machine (a shape, not a specification).

SMMU / IOMMU · Week 6, security in Week 7 — A translation stage in front of every device transaction, so each device sees only its own mapped pages. In Week 6 a convenience; in Week 7 the difference between “a compromised Wi-Fi or modem firmware can read your DRAM” and “it cannot.”

Soak · Week 5; protocol in Appendix C — A long sustained-load run held past the thermal transient. A soak curve has three phases nameable on sight: the burst (full clock, nothing hot yet), the knee (skin temperature approaches the limit, the governor steps down, delivered work falls off a cliff), and the sustained state (power settles, the clock hunts between adjacent operating points forever). That is the machine; everything before was a transient.

SoC (system-on-chip) · Week 1 — System on a chip: not a CPU with peripherals but a substantial fraction of an entire computer — a dozen or more independent processors, several programmable, several running their own operating systems, most able to issue memory transactions on their own behalf. Integration means sharing.

SoC Architecture Review · begun Week 1, finished in the capstone — The running document submitted as soc-architecture-review.docx: one real SoC block by block, CPU cluster and memory configurations, primary-source citations for every figure, and a bottleneck prediction for named workloads. Students who write a real document in Week 1 have a capstone that is half done.

Specialization · Week 4 — Building hardware shaped like the problem, because inside a fixed power budget the only way to do more work is to make each unit cost fewer joules. An accelerator is not faster arithmetic; it is less overhead and less data movement. The cost side: every fixed-function block narrows what the chip is good at and sits dark most of the time.

Specify the seam · Week 6 — The unglamorous answer to interface failure: for each interface write down the data format, buffer ownership and lifetime, the latency and throughput contract, the deadline if any, the error semantics, and the versioning rule — then instrument it with a transaction counter, a latency histogram, a deadline-miss count. An interface you cannot observe is one you cannot debug.

Spectre and Meltdown · Week 7 — Meltdown (CVE-2017-5754) and Spectre (v1, CVE-2017-5753; v2, CVE-2017-5715), disclosed January 2018, affecting many out-of-order cores across vendors including some Arm Cortex-A designs, for which Arm published a list. Mechanism: a core speculates past a check, does work it should not have, and correctly rolls back architectural state — but not microarchitectural state, which an attacker reads out of the cache. What was attacked was not a coding error but a performance feature working exactly as designed.

Speculation · Week 1 — Executing work before you know it is needed. Its mobile framing is a sentence worth carrying beyond branches: “it ran and we threw it away.” The same shape covers a prefetch of the wrong line, a frame rendered then composited over, a sensor sample discarded, a radio wake with nothing to send. When hunting energy, look first for work performed correctly and then thrown away.

Steady state · Week 8 — Two of them, and they are different claims. Microarchitectural steady state arrives in milliseconds — caches warm, predictor trained, clocks boosted. Thermal steady state arrives in minutes, and it is lower. Say which one your claim is about.

Superscalar · Week 1 — Issuing more than one instruction per cycle when more than one is ready. Note the condition: a dependency chain starves a wide core of issue slots it already paid for.

Sustained · Week 5 — What a device delivers at thermal steady state, once the chassis has stopped absorbing heat: the right claim for a game, an export, a navigation session, a long generation. Peak and sustained are not two estimates of one quantity; they are answers to two different questions.

Sustained/peak ratio · Week 8 — Report it as a first-class result: a compact statement about a design’s thermal honesty, often more informative than either raw score. A part leading on peak and trailing on this ratio spends its thermal budget early — defensible for a bursty product, wrong for a sustained one.

SVE / SVE2 · Week 1 — Arm’s vector-length-agnostic SIMD, an Armv9-A baseline. The hardware vector length is an implementation choice from 128 to 2048 bits in 128-bit increments, and the same binary runs correctly at any of them — the same bytes, not recompiled — because the loop is written against a predicate and an increment rather than a hard-coded width, so there is no scalar tail. On a 128-bit implementation SVE and NEON perform similarly; the gain is not in the instructions, it is in deployment.

Synthetic teaching data · course-wide; provenance in Appendix B — Data authored to reproduce the shape of published behaviour rather than measured from a product, carrying as its first line # SYNTHETIC TEACHING DATA — modeled on published behavior, not a measurement of any specific product. You may cite the shape. You may not cite the numbers, and any submission built on one must say so and say what it limits.

System-level cache (SLC) · Week 3 — A cache in front of the memory controller, shared by CPU, GPU, NPU, display and ISP alike. It is not an L3: the L3 behind the DSU serves the CPU cluster, while the SLC serves everybody, primarily to keep traffic off the DRAM pins — an energy decision before a performance one.

T

Tail (radio tail) · Week 6 — The period after your last byte during which the standards keep a radio connection in a high-power state, because tearing it down and rebuilding it would cost more. 3GPP structures this as connection states — connected, idle, and in 5G NR an intermediate inactive state — with discontinuous reception letting the device doze between listening windows. Timers are operator-configured; do not quote them. The universal shape: a radio is billed per second awake, not per byte, which is why batching beats compressing.

TBDR (tile-based deferred rendering) · Week 4 — Tile-based rendering that resolves visibility before shading, so hidden fragments are never shaded. Imagination’s PowerVR is the classic TBDR architecture and Apple’s GPUs are TBDR. Note precisely what it saves: ALU cycles, texture fetches and their energy — not the DRAM traffic of the final colour resolve, which was already one write per pixel. Two savings, two mechanisms; do not conflate them.

Thermal envelope · Week 5 — Sustained dissipation, roughly ΔT / R_thermal: how much hotter than the room you may be, divided by how hard it is to get heat out. Raising ambient shrinks the numerator, which is why a device is slower in a hot car, in sun, or in a case.

Thermal headroom · Week 5 — Android’s getThermalHeadroom(int forecastSeconds), returning a normalized forecast of how close the device will be to throttling, where 1.0 is the throttling threshold. Both choices are deliberate: normalizing hides device-specific temperatures an app could not compare anyway, and forecasting exists because by the time temperature is at the limit you are already late.

Thermal mass · Week 5 — The chassis’s heat capacity, absorbing energy while its temperature rises: T(t) = T_ambient + R·P·(1 − e^(−t/τ)), with τ = R · C_thermal. Everything about mobile benchmarking follows from the existence of τ — a cold device is one with its whole thermal budget unspent, which is why a benchmark’s first run is fast and its tenth is not.

Thermal path · Week 5 — Die → package → thermal interface material and a vapour chamber or graphite spreader → chassis → convection and radiation off the surface. Every stage is a resistance and the last is a bad one: a smooth surface, still air, a modest temperature difference. A block diagram tells you what the chip can do; a thermal path tells you how long it can do it.

Thermal status · Week 5 — Android’s ladder from PowerManager.getCurrentThermalStatus() and addThermalStatusListener(): THERMAL_STATUS_NONE, LIGHT, MODERATE, SEVERE, CRITICAL, EMERGENCY, SHUTDOWN. The architectural point is what it admits: the platform cannot manage the thermal budget alone, because only the application knows which of its work is discretionary. Thermal management is a hardware/software contract.

Threat model · Week 7 — The named adversaries with named capabilities: remote software attacker, malicious application, network attacker, physical possession, supply-chain attacker. Write it before the mechanism list. Everyone can recite “secure boot, TEE, hardware keys”; few can say which adversary each stops and which it does nothing about. A mechanism without a named adversary is a feature, not a defence.

Three C’s · Week 3 — The miss taxonomy, still the fastest diagnostic vocabulary in the field. Compulsory (cold): first touch of a line, reducible only by prefetching or touching less data. Capacity: the working set exceeds the level — the miss that draws the staircase. Conflict: the data fits but too many needed lines map to one set, entirely an artifact of the indexing scheme.

Throttling · Week 5 — Reducing clocks and voltage to hold a surface at a temperature a person can tolerate. It is not a defect — a device that did not throttle under heavy sustained load would be a device that burned someone. The question is never “why is it throttling” but what is the sustained envelope, and did we design for that or for the transient?

Tier (Normal / Medium / Hard) · every lab; rubrics in Appendix D — Normal is the measurement and analysis, and every Normal-tier requirement in this book is completable on Workbench B alone. Medium extends the experiment for extra credit. Hard is always a written architecture memo committing to a recommendation and pricing it — the judgment no tool produces for you, and the point of the course.

Tile-based rendering · Week 4 — The mobile GPU idea. Divide the frame into tiles small enough that colour and depth fit in on-chip tile memory; bin the geometry per tile; render each tile entirely on-chip; write only the finished colour to DRAM — the depth buffer normally never leaves the chip at all. The saving is bytes to DRAM, therefore energy, and pixel-side traffic stops scaling with overdraw. It is a trade: per-pixel traffic exchanged for per-triangle bin traffic, so a geometry-dense, overdraw-free frame is where the advantage shrinks and can invert.

Tile memory · Week 4 — The fast on-chip storage a tile renders into. Anything forcing its contents to DRAM — a read-back, an unnecessary load or clear of a render target — undoes the architecture in one API call.

TLB · Week 3 — The cache of virtual-to-physical translations. A miss triggers a hardware page-table walk — several dependent accesses, each of which can itself miss — so a TLB miss can cost more than an ordinary cache miss. Reason with TLB reach = entries × page size: exceed it and you walk on nearly every access no matter how well your data caches are doing.

Tool landscape · Week 8 — Know the real names: Arm Performance Studio — the suite, with Streamline (system profiler), Mali Offline Compiler, Frame Advisor and Performance Advisor, at https://developer.arm.com/; Perfetto for Android and Linux tracing, at https://perfetto.dev/, which deprecates systrace; simpleperf, Android’s perf-equivalent sampling profiler with PMU access; Android Studio Profiler; Android GPU Inspector (AGI); the Jetpack Microbenchmark and Macrobenchmark libraries, which encode this chapter’s hygiene rules as enforced behaviour rather than advice; perf on Linux; Instruments and xctrace on Apple platforms; and portable C++ steady_clock everywhere, which is why every lab runs on Workbench B.

TOPS · Week 4, dismantled in Week 8 — Tera-operations per second: MAC units × operations per unit per cycle × clock. Arithmetic about the hardware’s shape, not a measurement of anything running. Four questions dismantle any TOPS claim: at what precision (a number without a datatype is not a number), at what utilization, sustained for how long, with what memory system behind it. TOPS is not a lie; it is an incomplete claim presented in a context that invites a complete reading.

Translation granule · Week 3 — AArch64’s architected page sizes: 4 KB, 16 KB, 64 KB. Apple platforms use 16 KB; mainline Android and Linux have historically used 4 KB with 16 KB support arriving in recent generations — generation-dependent, so check your target’s documentation. Quadrupling the granule quadruples TLB reach and shortens the walk; it also coarsens allocation and increases internal fragmentation.

Trusted execution environment (TEE) · Week 7 — An isolated environment for sensitive code — key handling, DRM, biometric matching. On Arm it is realized with TrustZone: a small trusted OS on the same cores, sharing the same caches, predictors, prefetchers and memory bus with the Normal world, which is its structural weakness. A TEE protects the assets you actually put inside it — an asset cached in a normal-world process for convenience is protected by the boundary it is behind at the moment of attack, not the one it was born behind.

TrustZone · Week 1, developed Week 7 — Arm’s partition into a Secure world and a Non-secure (Normal) world. It is not merely a CPU mode: the NS bit propagates onto the interconnect, so memory, peripherals and DMA masters are partitioned too. A CPU mode protects you from code on that CPU; a system partition protects you from every master on the fabric, including engines that never execute an instruction of yours.

U

UCIe · Week 8 — The industry standard effort for die-to-die interconnect, alongside the chiplet vocabulary of 2.5D interposers, 3D stacking and package-on-package DRAM. Be careful with adoption claims in phone SoCs specifically.

uclamp · Week 2 — Utilization clamping: a floor or ceiling on a task’s perceived utilization — “treat this as busier than it looks,” or “never let this look busy enough to justify a big core.” It is also the mechanism by which a well-meaning engineer forces background work onto performance cores and ships worse battery life with no visible gain.

UFS · Week 3 — The mobile storage interface: serial, full-duplex, with command queuing — contrast the older half-duplex eMMC. UFS 4.0 (2022) roughly doubled the per-lane rate over UFS 3.1, with real-world sequential reads in the low single-digit GB/s; hedge all of that and check the part.

Unified memory architecture · Week 3 — CPU, GPU and NPU sharing one physical memory behind one controller. The win is the copy you do not make — the difference between a feasible camera pipeline and an infeasible one. The cost is that everything now contends: one bandwidth budget, one power budget, one thermal budget, with the display controller outranking you. Unified memory removes a copy and adds a queue — whether that is a win depends on whether your workload was copy-bound or bandwidth-bound, so say which and how you know.

Useful bytes per line · Week 3 — Bytes your program consumes ÷ bytes the line delivered. Read one 4-byte float from a 64-byte line and use nothing else and the ratio is 6.25% — a full transaction and its full energy for a sixteenth of its value, in a loop, while every profiler reports the core busy. The single most useful number for arguing about data layout.

Utilization · Week 8 — The fraction of wall-clock time the scheduler had a runnable thread on a core rather than parking it idle. A time measure, not a work measure: a core stalled hundreds of cycles on a DRAM round trip counts as fully busy. Hence: a core reported at 100% utilization may be doing nothing at all. The fix is a discipline — pair every utilization number with an IPC and a miss rate. High/high/low is genuinely compute-bound; high/low/high is memory-bound; high/low/low suggests a dependency chain, a lock or mispredicted branches; low means something upstream is not feeding it.

V

Vector-length agnostic (VLA) · Week 1 — The property, shared by SVE/SVE2 and RVV, that the same binary runs correctly and at full width on hardware of any supported vector length, because the loop is written against a predicate (or a returned element count) rather than a hard-coded width. The most important ISA idea in this course, and for a non-microarchitectural reason: where you cannot recompile for every device your binary will land on — every shipped mobile application, framework and system library — VLA converts “target the narrowest device” into “use whatever width we find.” An ecosystem win.

Verified boot · Week 7 — Android’s secure-boot implementation, adding a reported boot state and rollback protection. Stated narrowly, its promise is that however badly today went, a reboot returns you to code the vendor signed. Precision about what a mechanism covers is most of what separates a threat model from a brochure.

Video codec block · Week 4 — Fixed-function encode and decode for standardized bitstreams (H.264, HEVC, AV1), because the same codec in software burns orders of magnitude more energy — on a phone, whether the battery survives a video call. AV1 decode is broadly present in recent flagship mobile silicon; AV1 encode in hardware is less widespread, so check the part. Entropy coding is serial and bit-exact and is simply not a tensor graph, so an NPU is not an alternative here.

Virtual memory · Week 3 — Per-process address spaces translated through multi-level page tables the hardware itself walks, with the TLB caching translations. In Week 7 the same machinery is re-read as the device’s primary memory-safety mechanism, extended to devices by the SMMU.

volatile · Week 6 — Tells the compiler that every access in the source must appear in the object code, exactly as often, in this order relative to other volatile accesses. Necessary at a device boundary and insufficient twice over: it is not a memory barrier (it constrains the compiler, not the hardware) and it is not a concurrency primitive (no atomicity, no inter-processor ordering — between CPUs use std::atomic with real acquire/release semantics). Using it for a shared flag is a bug that happens to work on some machines, which is the worst kind.

Voltage sag · Week 5 — The drop in a cell’s terminal voltage under load, worsening as the cell depletes and as it gets cold. With capacity fade over cycles it is why nominal voltage is an average and why a two-year-old device works with a smaller budget than its spec sheet describes.

W

Wake-up · Week 5 and Week 6 — Pulling a core or subsystem out of a low-power state, costing exit latency and energy and possibly lighting up the memory controller or the radio behind it. Ten background apps checking in once a minute on their own schedules cost far more than the same ten together every ten minutes: same bytes, one wakeup instead of sixty. When you design an interface between a fast thing and a sleepy thing, the question is never “how do I make each event cheaper?” but “how few times must the sleepy thing wake up?”

WALT — See PELT.

Warm-up · Week 8 — The discarded first iterations. The first run of anything measures cold caches, an untrained predictor, unfaulted pages, and a core still at a low operating point because the governor has not noticed you exist.

Warp / wavefront / wave — See Lockstep group.

Watt-hour (Wh) · Week 5 — Battery energy: Wh = mAh × nominal volts / 1000, and 1 Wh = 3600 J. It is the comparable number across devices, which is why regulators and airlines ask for it.

Weight footprint · Week 3 — parameters × bytes-per-weight, exact arithmetic. It decides feasibility, and it is a floor: real total memory is weights plus KV cache plus activations plus runtime plus framework plus the OS’s own needs, on a device that kills processes rather than swapping. Fitting and being fast are different questions.

Workbench · defined in Appendix A — Workbench L (Local): a laptop with a C++17 compiler and Python 3; the default. Workbench B (Browser): a cloud development environment with no install and no administrator rights — every Normal-tier requirement in this book is completable on Workbench B alone, so a student with a locked-down Chromebook and an iPhone can earn 100. Workbench D (Device): Workbench L plus an Android device with developer options and the debug bridge; always optional, appearing only in Medium and Hard tiers and in clearly labelled go-further steps.

Working set · Week 3 — The bytes a program actively touches over a window of time. Sweeping it while timing accesses is how you infer a cache hierarchy from your own machine: flat regions are levels, steps are capacity boundaries, and every inferred boundary is a hypothesis with evidence behind it, not a datasheet reading.

X · Y · Z

XR (extended reality) · Week 8 — The form factor with the hardest constraint in consumer computing: a hard, low motion-to-photon budget under a thermal and weight limit sitting on a human face, which is why some products split work between the headset and a tethered puck or phone.

Zero register · Week 1 — XZR/WZR: reads as zero and discards writes. Encoding-wise it occupies the same slot as the stack pointer in some instruction forms — worth knowing the first time an assembly listing surprises you.

Using this page

Look up the word you are about to write, not the word you did not know. The terms that cost marks are the familiar ones used in the wrong sense: bandwidth for latency, power for energy, utilization for performance. Before you commit a sentence containing one of the ten pairs, check that the entry says what you are about to say.

Carry the conditions with the word. Half the entries above end in a clause about what a term does not commit anyone to, and that clause is the professional content. “Sustained” without its window, “accelerated” without its operator report, “secure” without an asset and an adversary, TOPS without a datatype — each is a word doing less work than it appears to. Appendix C turns that habit into a template and Appendix D turns it into a rubric.

And when a definition and a datasheet disagree, believe the datasheet. This page gives you the shape of things and the ranges the field currently sits in. It deliberately declines to name a cache size, a clock, a bus width or a TOPS rating for any real part, because those figures must come from a primary source or from your own measurement with its conditions attached. That refusal is not a limitation of the glossary. It is the course.