Eight Weeks Inside the Machine in Your Pocket

Mobile Computer Architecture

COACH

DR. MICHAEL LITMAN, PH.D.

Master Computer Scientist

A desktop architect asks how fast it can go. A mobile architect asks four questions at once — how fast, at what energy, for how long before it throttles, and on which processor. Master those four and the whole strange shape of a phone becomes obvious.

8
Weeks
7
Graded labs
4
Recurring questions
1
Capstone SoC study

An eight-week graduate course in the architecture of phones, tablets, wearables, and XR headsets — the systems that made specialization, energy, and heat the first-order design constraints of modern computing. You start at the instruction set and the system-on-chip block diagram, work through heterogeneous multicore CPUs, the memory hierarchy that decides most of your performance, and the fleet of accelerators that surrounds the CPU. Then the week that reframes everything: power, battery, and thermals — why a phone benchmarks brilliantly for ninety seconds and then does not. Integration, sensors, and radios follow; then hardware security from the root of trust up; then a final week on measuring honestly, comparing real silicon, and the systems coming next. Roughly sixty percent architecture, twenty-five percent hands-on measurement, fifteen percent emerging technology — and the capstone is an architecture investigation, not an app.

SYLLABUS

Part One

Week 1
Ch 1 — The Machine in Your Pocket
What makes mobile architecture a different discipline — battery, heat, size, always-on operation, radios and sensors; the system-on-chip and every block on it; AArch64 registers, instruction execution, and exception levels; reduced versus complex instruction sets; ARM against x86 and RISC-V; pipelining, superscalar and out-of-order execution, branch prediction; single-instruction-multiple-data with NEON, SVE2, and the RISC-V vector extension; and how to read a real Snapdragon, Apple, MediaTek, or Google block diagram
P1The SoC Teardown
Week 2
Ch 2 — Not All Cores Are Equal
Heterogeneous multicore as the defining idea of modern mobile computing: performance cores against efficiency cores, big.LITTLE and DynamIQ, homogeneous versus heterogeneous multiprocessing, thread migration and affinity, hardware and software scheduling, frequency and voltage scaling, single-thread against multicore performance, sustained against burst, cache coherence between unlike cores, and performance-per-watt as the metric that decides the design
P2The Placement Study
Week 3
Ch 3 — The Real Bottleneck
Why an algorithm with fewer instructions can still lose: registers and the L1/L2/L3 hierarchy, hits, misses, locality and replacement, shared versus private caches and coherence, LPDDR main memory, bandwidth against latency, unified and shared memory architectures, virtual memory, page tables and translation lookaside buffers, memory-mapped input/output and direct memory access, why moving data costs more energy than computing on it, memory pressure on a phone, and NAND and UFS storage
P3The Memory Wall Lab
Week 4
Ch 4 — Beyond the CPU
The accelerator fleet and why mobile silicon went heterogeneous: CPU against GPU against NPU against DSP, single-instruction-multiple-thread and massive parallelism, mobile GPU architecture, tile-based rendering, shader cores and the graphics pipeline, general-purpose GPU compute, neural processing units and matrix math, quantization from thirty-two-bit float down to eight-bit integer and below, on-device artificial intelligence inference, partitioning a workload across processors, image signal processors, and hardware video encode and decode — plus the midterm checkpoint
Midterm Checkpoint & Placement Practical

Part Two

Week 5
Ch 5 — The Budget That Governs Everything
The week that reframes the whole course: dynamic against static power, the relationship among voltage, frequency and power, dynamic voltage and frequency scaling, clock gating, power gating, sleep states, race-to-idle, performance-per-watt, battery characteristics and energy budgets, thermal design power against a mobile thermal envelope, throttling, sustained against peak performance, how an operating system responds to thermal stress, and energy-aware scheduling
P5The Energy and Thermal Study
Week 6
Ch 6 — Wiring the System Together
Everything outside the compute blocks: SoC buses and interconnects, memory-mapped peripherals, interrupts, direct memory access revisited, USB and PCIe where they appear, display controllers, touch, cameras, accelerometer, gyroscope, magnetometer and satellite positioning, sensor hubs and always-on processors, Bluetooth and Wi-Fi architecture, the cellular modem as an SoC subsystem, fifth-generation cellular at the level an architect needs, the hardware and software boundary, hardware abstraction layers, and interrupt-driven against polled designs
P6The Integration Map
Week 7
Ch 7 — Trust in Silicon
Hardware security from the root of trust upward: the threat model for a device that leaves the building, secure and verified boot, trusted execution environments, TrustZone and the secure and normal worlds, privilege and exception levels, memory protection, hardware-backed keys, biometrics and secure processors, cryptographic acceleration, memory tagging, side-channel attacks, Spectre- and Meltdown-class architectural vulnerabilities, physical against software attacks, secure enclaves and secure elements, and post-quantum cryptography as an emerging mobile workload
P7The Silicon Threat Model
Week 8
Ch 8 — Measure, Compare, Decide
Benchmarking correctly and the architecture judgment it serves: microbenchmarks against application benchmarks, utilization against actual performance, instructions per cycle, cache-miss and branch-miss rates, memory bandwidth, GPU utilization, throttling, power measurement, profilers and hardware performance counters, ARM Performance Studio and the Android tooling, comparing real silicon, and where mobile systems are going — phones against tablets against headsets against wearables, edge artificial intelligence, RISC-V application processors, chiplets and advanced packaging, and ever more specialized accelerators
P8The Capstone SoC Investigation